25 search results - page 4 / 5 » Global Multi-Threaded Instruction Scheduling |
ASPLOS
1992
ACM
14 years 20 days ago
1992
ACM
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
ASPLOS
2006
ACM
14 years 2 months ago
2006
ACM
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
LCTRTS
2001
Springer
14 years 1 months ago
2001
Springer
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
EGH
2005
Springer
14 years 2 months ago
2005
Springer
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...