Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
We study the performance of packet routing on arrays (or meshes) with bounded buffers in the routing switches, assuming that new packets are continuously inserted at all the nodes....
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
This paper introduces VTsim, a device simulator for Xilinx Virtex-II FPGAs. VTsim is currently a globally synchronous event-driven device simulator modeled at the CLB level. Throu...
The Time Warp protocol is considered to be an effective synchronization mechanism for parallel discrete event simulation (PDES). However, it is widely recognized that it suffers o...