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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
14 years 29 days ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
LATIN
1998
Springer
14 years 28 days ago
Dynamic Packet Routing on Arrays with Bounded Buffers
We study the performance of packet routing on arrays (or meshes) with bounded buffers in the routing switches, assuming that new packets are continuously inserted at all the nodes....
Andrei Z. Broder, Alan M. Frieze, Eli Upfal
ICCD
1992
IEEE
82views Hardware» more  ICCD 1992»
14 years 24 days ago
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
Erik Brunvand, Nick Michell, Kent F. Smith
ERSA
2004
192views Hardware» more  ERSA 2004»
13 years 10 months ago
VTSim: A Virtex-II Device Simulator
This paper introduces VTsim, a device simulator for Xilinx Virtex-II FPGAs. VTsim is currently a globally synchronous event-driven device simulator modeled at the CLB level. Throu...
Jesse Hunter, Peter Athanas, Cameron Patterson
WSC
1998
13 years 10 months ago
Combining Optimism Limiting Schemes in Time Warp Based Parallel Simulations
The Time Warp protocol is considered to be an effective synchronization mechanism for parallel discrete event simulation (PDES). However, it is widely recognized that it suffers o...
Kevin G. Jones, Samir Ranjan Das