Sciweavers

104 search results - page 15 / 21
» Globally Asynchronous Locally Synchronous FPGA Architectures
Sort
View
CF
2010
ACM
14 years 14 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
DAC
2001
ACM
14 years 8 months ago
Transformations for the Synthesis and Optimization of Asynchronous Distributed Control
Asynchronous design has been the focus of renewed interest. However, a key bottleneck is the lack of high-quality CAD tools for the synthesis of large-scale systems which also all...
Michael Theobald, Steven M. Nowick
TCAD
2008
90views more  TCAD 2008»
13 years 7 months ago
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design
Due to the increasing abstraction gap between the initial system model and a final implementation, the verification of the respective models against each other is a formidable task...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
IPPS
2010
IEEE
13 years 4 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 7 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside