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» Good Programming in Transactional Memory
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ASPLOS
1992
ACM
13 years 11 months ago
Closing the Window of Vulnerability in Multiphase Memory Transactions
Multiprocessor architects have begun to explore several mechanisms such as prefetching, context-switching and software-assisted dynamic cache-coherence, which transform single-pha...
John Kubiatowicz, David Chaiken, Anant Agarwal
ASPLOS
2004
ACM
14 years 29 days ago
Programming with transactional coherence and consistency (TCC)
Transactional Coherence and Consistency (TCC) offers a way to simplify parallel programming by executing all code within transactions. In TCC systems, transactions serve as the fu...
Lance Hammond, Brian D. Carlstrom, Vicky Wong, Ben...
DC
2010
13 years 7 months ago
Model checking transactional memories
Model checking software transactional memories (STMs) is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memo...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
14 years 1 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
ASPLOS
2009
ACM
14 years 8 months ago
Early experience with a commercial hardware transactional memory implementation
We report on our experience with the hardware transactional memory (HTM) feature of two pre-production revisions of a new commercial multicore processor. Our experience includes a...
David Dice, Yossi Lev, Mark Moir, Daniel Nussbaum