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CDES
2010
184views Hardware» more  CDES 2010»
13 years 6 months ago
Delay-Insensitive Cell Matrix
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
Scott Smith, David Roclin, Jia Di
INFOCOM
2002
IEEE
14 years 1 months ago
Power-Saving Protocols for IEEE 802.11-Based Multi-Hop Ad Hoc Networks
—Power-saving is a critical issue for almost all kinds of portable devices. In this paper, we consider the design of power-saving protocols for mobile ad hoc networks (MANETs) th...
Yu-Chee Tseng, Chih-Shun Hsu, Ten-Yueng Hsieh
ISLPED
2010
ACM
169views Hardware» more  ISLPED 2010»
13 years 6 months ago
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Abstract--As a replacement for the fast-fading GloballySynchronous model, we have defined a flexible design style called GRLS, for Globally-Ratiochronous, Locally-Synchronous, whic...
Jean-Michel Chabloz, Ahmed Hemani
SPIN
2000
Springer
14 years 6 days ago
Modeling the ASCB-D Synchronization Algorithm with SPIN: A Case Study
In this paper, we describe our application of SPIN 1 to model an algorithm used to synchronize the clocks of modules that provide periodic real-time communication over a network. W...
Nicholas Weininger, Darren D. Cofer
FOSSACS
2010
Springer
14 years 3 months ago
The Complexity of Synchronous Notions of Information Flow Security
The paper considers the complexity of verifying that a finite state system satisfies a number of definitions of information flow security. The systems model considered is one i...
Franck Cassez, Ron van der Meyden, Chenyi Zhang