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IPPS
2000
IEEE
14 years 1 days ago
Performance of On-Chip Multiprocessors for Vision Tasks
Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available...
Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Vi...
ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
13 years 12 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
COMPUTER
2002
103views more  COMPUTER 2002»
13 years 7 months ago
SimpleScalar: An Infrastructure for Computer System Modeling
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
Todd M. Austin, Eric Larson, Dan Ernst
ASPLOS
2006
ACM
14 years 1 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
INFOCOM
2009
IEEE
14 years 2 months ago
Network Bandwidth Allocation via Distributed Auctions with Time Reservations
—This paper studies the problem of allocating network capacity through periodic auctions. Motivated primarily by a service overlay architecture, we impose the following condition...
Pablo Belzarena, Andrés Ferragut, Fernando ...