Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Clusters of workstations have emerged as an important platform for building cost-effective, scalable, and highlyavailable computers. Although many hardware solutions are available...
Eitan Frachtenberg, Fabrizio Petrini, Juan Fern&aa...
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...