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DAC
2004
ACM
16 years 4 months ago
Profile-guided microarchitectural floorplanning for deep submicron processor design
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
187
Voted
VLDB
2005
ACM
132views Database» more  VLDB 2005»
16 years 3 months ago
Hash-based labeling techniques for storage scaling
Scalable storage architectures allow for the addition or removal of storage devices to increase storage capacity and bandwidth or retire older devices. Assuming random placement of...
Shu-Yuen Didi Yao, Cyrus Shahabi, Per-Åke Larson
130
Voted
AINA
2007
IEEE
15 years 9 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
131
Voted
IPPS
2007
IEEE
15 years 9 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
129
Voted
ICDCSW
2003
IEEE
15 years 8 months ago
Scaling Server Selection Using a Multi-Broker Architecture
Server replication is a common approach to improving the scalability of a service on the Internet. For this approach, the task of finding an appropriate server from a set of repli...
Mohamed-Vall O. Mohamed-Salem, Gregor von Bochmann...