112 search results - page 14 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
ARCS
2010
Springer
13 years 7 months ago
2010
Springer
Processor speed and available computing power constantly increases, enabling computation of more and more complex problems such as numerical simulations of physical processes. In t...
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
The solution to a set of sparse linear equations Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained using the W-matrix method. An enhanced vect...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— A VLSI hardware architecture for the on-chip implementation of a first-order 3D IIR fully-multiplexed frequencyplanar filter module (FMFPM) is proposed. FMFPMs may be employed ...
ISPAN
2005
IEEE
14 years 1 months ago
2005
IEEE
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
3DIM
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes a fast, simultaneous alignment method for a large number of range images. Generally the most time-consuming task in aligning range images is searching corresp...