A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics

Processor speed and available computing power constantly increases, enabling computation of more and more complex problems such as numerical simulations of physical processes. In this domain, however, the problem of accuracy arises due to rounding of intermediate results. One solution is to avoid intermediate rounding by using exact arithmetic. The use of FPGAs as application-specific accelerators can speed up such operations compared to their software implementation. In this paper, we present a system approach employing state-of-the art FPGA and interconnection technology for exact arithmetic with doubleprecision operands, delivering up to 400M exact MACs/s in total and providing a speedup of up to 88 times over competing software implementations in the case of matrix multiplication.

• Type: Conference
• Year: 2010
• Where: ARCS
• Authors: Fabian Nowak, Rainer Buchty
• Keywords: ARCS 2010, Exact Arithmetic, Intermediate Rounding, Software Engineering, Software Implementations