112 search results - page 7 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
FCCM
2009
IEEE
14 years 2 months ago
2009
IEEE
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
EVOW
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. The efficient design of multiplierless implementations of constant matrix multipliers is challenged by the huge solution search spaces even for small scale problems. Prev...
ARC
2012
Springer
12 years 3 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
ARC
2010
Springer
14 years 2 months ago
2010
Springer
Dot-products are one of the essential and recurrent building blocks in scientific computing, and often take-up a large proportion of the scientific acceleration circuitry. The ac...
FPL
2011
Springer
12 years 7 months ago
2011
Springer
—On-chip Physical Unclonable Functions (PUFs) are emerging as a powerful security primitive that can potentially solve several security problems. A PUF needs to be robust against...