Sciweavers

794 search results - page 158 / 159
» Hardware Natural Language Interface
Sort
View
TVLSI
2008
187views more  TVLSI 2008»
13 years 7 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
SC
2000
ACM
13 years 12 months ago
Performance of Hybrid Message-Passing and Shared-Memory Parallelism for Discrete Element Modeling
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...
D. S. Henty
CF
2005
ACM
13 years 9 months ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
ECCC
2010
98views more  ECCC 2010»
13 years 5 months ago
Efficient Semantic Communication via Compatible Beliefs
In previous works, Juba and Sudan [6] and Goldreich, Juba and Sudan [4] considered the idea of "semantic communication", wherein two players, a user and a server, attemp...
Brendan Juba, Madhu Sudan
SPAA
2009
ACM
14 years 8 months ago
A lightweight in-place implementation for software thread-level speculation
Thread-level speculation (TLS) is a technique that allows parts of a sequential program to be executed in parallel. TLS ensures the parallel program's behaviour remains true ...
Cosmin E. Oancea, Alan Mycroft, Tim Harris