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CHARME
1995
Springer
120views Hardware» more  CHARME 1995»
13 years 11 months ago
Timing analysis of asynchronous circuits using timed automata
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
Oded Maler, Amir Pnueli
ICCAD
1995
IEEE
129views Hardware» more  ICCAD 1995»
13 years 11 months ago
Activity-driven clock design for low power circuits
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
Gustavo E. Téllez, Amir H. Farrahi, Majid S...
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
13 years 11 months ago
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays
We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a xed cut line sequence that is determined before min...
Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai...
WSC
2007
13 years 10 months ago
A co-design modeling approach for computer network systems
Co-design modeling is considered key toward handling the complexity and scale of network systems. The ability to separately specify the software and hardware aspects of computer n...
Weilong Hu, Hessam S. Sarjoughian
ASPDAC
2008
ACM
93views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Scheduling with integer time budgeting for low-power optimization
In this paper we present a mathematical programming formulation of the integer time budgeting problem for directed acyclic graphs. In particular, we formally prove that our constr...
Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason C...