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FCCM
2007
IEEE
122views VLSI» more  FCCM 2007»
13 years 11 months ago
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
DELTA
2006
IEEE
13 years 11 months ago
Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmabl
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
Peter J. Green, Desmond P. Taylor
IFIPTCS
2000
13 years 11 months ago
Masaccio: A Formal Model for Embedded Components
Masaccio is a formal model for hybrid dynamical systems which are built from atomic discrete components (di erence equations) and atomic continuous components (di erential equation...
Thomas A. Henzinger
SIGOPSE
1994
ACM
13 years 11 months ago
New Directions for Integrated Circuit Cards Operating Systems
Integrated circuit cards or smart cards are now well-known. Applications such as electronic purses (cash units stored in cards), subscriber identification cards used in cellular te...
Pierre Paradinas, Jean-Jacques Vandewalle
ASPLOS
2010
ACM
13 years 11 months ago
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems
Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantl...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....