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» Hardware Reuse at the Behavioral Level
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CGO
2006
IEEE
13 years 11 months ago
Profiling over Adaptive Ranges
Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. This p...
Shashidhar Mysore, Banit Agrawal, Timothy Sherwood...
FPL
2010
Springer
108views Hardware» more  FPL 2010»
13 years 5 months ago
FPGA Based Network Traffic Analysis Using Traffic Dispersion Patterns
The problem of Network Traffic Classification (NTC) has attracted significant amount of interest in the research community, offering a wide range of solutions at various levels. Th...
Faisal Khan, Maya Gokhale, Chen-Nee Chuah
PPOPP
2010
ACM
14 years 2 months ago
Load balancing on speed
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
Steven Hofmeyr, Costin Iancu, Filip Blagojevic
SAMOS
2007
Springer
14 years 1 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...
IEEEPACT
2005
IEEE
14 years 28 days ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove