Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
We have implemented a set of computational physics codes on a network of IBM RS/6000 workstations used as a distributed parallel computer. We compare the performance of the codes ...
In future, the decreasing feature size and the reduced power supply will make it much more difficult to built reliable microprocessors. Economic pressure will most likely result in...
Bandwidth demands of communication networks are rising permanently. Thus, the requirements to modern routers regarding packet classification are rising accordingly. Conventional al...