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ASPLOS
2011
ACM
13 years 2 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
FPL
2005
Springer
100views Hardware» more  FPL 2005»
14 years 3 months ago
HAIL: A Hardware-Accelerated Algorithm for Language Identification
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
HPDC
1993
IEEE
14 years 2 months ago
An Analysis of Distributed Computing Software and Hardware for Applications in Computational Physics
We have implemented a set of computational physics codes on a network of IBM RS/6000 workstations used as a distributed parallel computer. We compare the performance of the codes ...
Paul D. Coddington
SAFECOMP
2007
Springer
14 years 4 months ago
Software Encoded Processing: Building Dependable Systems with Commodity Hardware
In future, the decreasing feature size and the reduced power supply will make it much more difficult to built reliable microprocessors. Economic pressure will most likely result in...
Ute Wappler, Christof Fetzer
BIOADIT
2006
Springer
14 years 2 months ago
Packet Classification with Evolvable Hardware Hash Functions - An Intrinsic Approach
Bandwidth demands of communication networks are rising permanently. Thus, the requirements to modern routers regarding packet classification are rising accordingly. Conventional al...
Harald Widiger, Ralf Salomon, Dirk Timmermann