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» Hardware Support for Priority Inheritance
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ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
14 years 20 days ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...
IPPS
2003
IEEE
14 years 2 months ago
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
SPAA
2004
ACM
14 years 2 months ago
Cache-oblivious shortest paths in graphs using buffer heap
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
Rezaul Alam Chowdhury, Vijaya Ramachandran
RTAS
2011
IEEE
13 years 14 days ago
Virtual-CPU Scheduling in the Quest Operating System
This paper describes the scheduling framework for a new operating system called “Quest”. The three main goals of Quest are to ensure safety, predictability and efficiency of ...
Matthew Danish, Ye Li, Richard West
CACM
2008
100views more  CACM 2008»
13 years 9 months ago
TxLinux and MetaTM: transactional memory and the operating system
TxLinux is the first operating system to use hardware transactional memory (HTM) as a synchronization primitive, and the first to manage HTM in the scheduler. TxLinux, which is a ...
Christopher J. Rossbach, Hany E. Ramadan, Owen S. ...