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» Hardware Synthesis from C C Models
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128
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VLSI
2005
Springer
15 years 9 months ago
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
This work addresses the problem of application mapping in networks-on-chip (NoCs) having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (So...
César A. M. Marcon, José Carlos S. P...
113
Voted
SIGMETRICS
1995
ACM
15 years 7 months ago
Talisman: Fast and Accurate Multicomputer Simulation
Talisman is a simulator that models the execution semantics and timing of a multicomputer. Talisman is unique in combining high semantic accuracy, high timing accuracy, portabilit...
Robert C. Bedichek
143
Voted
ICSE
2007
IEEE-ACM
15 years 10 months ago
The Future of Software Performance Engineering
Performance is a pervasive quality of software systems; everything affects it, from the software itself to all underlying layers, such as operating system, middleware, hardware, c...
C. Murray Woodside, Greg Franks, Dorina C. Petriu
127
Voted
CODES
2006
IEEE
15 years 9 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
125
Voted
SIGMETRICS
2008
ACM
15 years 3 months ago
Ironmodel: robust performance models in the wild
Traditional performance models are too brittle to be relied on for continuous capacity planning and performance debugging in many computer systems. Simply put, a brittle model is ...
Eno Thereska, Gregory R. Ganger