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DATE
2004
IEEE
109views Hardware» more  DATE 2004»
14 years 1 months ago
RTL Processor Synthesis for Architecture Exploration and Implementation
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
Oliver Schliebusch, Anupam Chattopadhyay, Rainer L...
SIGCOMM
2009
ACM
14 years 4 months ago
Building a fast, virtualized data plane with programmable hardware
Network virtualization allows many networks to share the same underlying physical topology; this technology has offered promise both for experimentation and for hosting multiple n...
Muhammad Bilal Anwer, Nick Feamster
DAC
2005
ACM
14 years 11 months ago
Automatic generation of customized discrete fourier transform IPs
This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving...
Grace Nordin, Peter A. Milder, James C. Hoe, Marku...
GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
14 years 4 months ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
CAV
2004
Springer
136views Hardware» more  CAV 2004»
14 years 1 months ago
JNuke: Efficient Dynamic Analysis for Java
JNuke is a framework for verification and model checking of Java programs. It is a novel combination of run-time verification, explicit-state model checking, and counter-example ex...
Cyrille Artho, Viktor Schuppan, Armin Biere, Pasca...