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» Hardware Synthesis from Term Rewriting Systems
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DRM
2004
Springer
14 years 2 months ago
Attacks and risk analysis for hardware supported software copy protection systems
Recently, there is a growing interest in the research community to use tamper-resistant processors for software copy protection. Many of these tamper-resistant systems rely on a s...
Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Tao ...
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Bitwidth-aware scheduling and binding in high-level synthesis
- Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifica...
Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, J...
BIRTHDAY
2010
Springer
13 years 6 months ago
Termination Graphs for Java Bytecode
To prove termination of Java Bytecode (JBC) automatically, we transform JBC to finite termination graphs which represent all possible runs of the program. Afterwards, the graph can...
Marc Brockschmidt, Carsten Otto, Christian von Ess...
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
14 years 1 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
CAV
2010
Springer
223views Hardware» more  CAV 2010»
14 years 23 days ago
RATSY - A New Requirements Analysis Tool with Synthesis
Formal specifications play an increasingly important role in system design-flows. Yet, they are not always easy to deal with. In this paper we present RATSY, a successor of the R...
Roderick Bloem, Alessandro Cimatti, Karin Greimel,...