1077 search results - page 4 / 216 » Hardware code generation from dataflow programs |
SCAM
2008
IEEE
14 years 1 months ago
2008
IEEE
Data-flow analysis is a common technique to gather program information for use in transformations such as register allocation, dead-code elimination, common subexpression elimina...
USENIX
2008
13 years 9 months ago
2008
Large-scale parallel dataflow systems, e.g., Dryad and Map-Reduce, have attracted significant attention recently. High-level dataflow languages such as Pig Latin and Sawzall are b...
MICRO
2012
IEEE
11 years 9 months ago
2012
IEEE
This article presents a general algorithm for transforming sequential imperative programs into parallel data-flow programs. Our algorithm operates on a program dependence graph i...
ISSS
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper we propose an embedded software design flow, which starts from an UML model and provides automatic mapping to other models like Simulink or finite-state machines (FS...