951 search results - page 42 / 191 » Hardware design experiences in ZebraNet |
MEMOCODE
2010
IEEE
13 years 5 months ago
2010
IEEE
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
ADHOC
2011
2011
RadiaLE: A framework for designing and assessing link quality estimators in wireless sensor networks
12 years 11 months ago
—Stringent cost and energy constraints impose the use of low-cost and low-power radio transceivers in large-scale wireless sensor networks (WSNs). This fact, together with the ha...
DEBU
2010
13 years 5 months ago
2010
Flash memory affects not only storage options but also query processing. In this paper, we analyze the use of flash memory for database query processing, including algorithms that...
ITC
2002
IEEE
14 years 18 days ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ECBS
2006
IEEE
14 years 1 months ago
2006
IEEE
Design patterns are an established means for building evolvable and maintainable object-oriented software. However, using them requires the developer’s extensive experience. A w...