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» Hardware design experiences in ZebraNet
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NSDI
2008
13 years 11 months ago
Efficiency Through Eavesdropping: Link-layer Packet Caching
The broadcast nature of wireless networks is the source of both their utility and much of their complexity. To turn what would otherwise be unwanted interference into an advantage...
Mikhail Afanasyev, David G. Andersen, Alex C. Snoe...
ASAP
2008
IEEE
120views Hardware» more  ASAP 2008»
13 years 11 months ago
Lightweight DMA management mechanisms for multiprocessors on FPGA
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
DFT
2005
IEEE
132views VLSI» more  DFT 2005»
13 years 11 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
ACMSE
2011
ACM
12 years 9 months ago
Targeting FPGA-based processors for an implementation-driven compiler construction course
This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the ...
D. Brian Larkins, William M. Jones
ICCAD
2006
IEEE
189views Hardware» more  ICCAD 2006»
14 years 5 months ago
Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems
Energy-efficiency and power-awareness for electronic systems have been important design issues in hardware and software implementations. We consider the scheduling of periodic ha...
Jian-Jia Chen, Tei-Wei Kuo