Low Power BIST Based on Scan Partitioning

A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test. 3-valued weights are employed to detect the r.p.r. faults. The key idea is to use a new scan partitioning technique and decoding methodology that exploits correlations in the weight sets to greatly reduce the hardware overhead for multiple weight sets and reduce the number of transitions during scan shifting. The proposed scheme is simple to implement and only constrains the partitioning of scan elements into scan chains and not the scan order thereby having minimal impact on routing. Consequently, the proposed scheme can be easily implemented in standard design flows used in industry. Experiments indicate the scheme can achieve 100% fault coverage and % to 9% scan power reduction with relatively small hardware overhead.

• Type: Conference
• Year: 2005
• Where: DFT
• Authors: Jinkyu Lee, Nur A. Touba
• Keywords: DFT 2005, Hardware Overhead, Scan, Scan Partitioning Technique, VLSI