Sciweavers

951 search results - page 94 / 191
» Hardware design experiences in ZebraNet
Sort
View
GLOBECOM
2009
IEEE
15 years 11 months ago
Development Framework for Implementing FPGA-Based Cognitive Network Nodes
—This paper identifies important features a cognitive radio framework should provide, namely a virtual architecture ware abstraction, an adaptive run-time system for managing co...
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris...
ICCAD
2007
IEEE
139views Hardware» more  ICCAD 2007»
15 years 11 months ago
Using functional independence conditions to optimize the performance of latency-insensitive systems
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
Cheng-Hong Li, Luca P. Carloni
PADS
2003
ACM
15 years 10 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
FCCM
2009
IEEE
121views VLSI» more  FCCM 2009»
15 years 11 months ago
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy
—Photodynamic therapy (PDT) is a method of treating cancer that combines light and light-sensitive drugs to selectively destroy cancerous tumours without harming the healthy tiss...
Jason Luu, Keith Redmond, William Lo, Paul Chow, L...
USENIX
2008
15 years 7 months ago
Cutting Corners: Workbench Automation for Server Benchmarking
A common approach to benchmarking a server is to measure its behavior under load from a workload generator. Often a set of such experiments is required-perhaps with different serv...
Piyush Shivam, Varun Marupadi, Jeffrey S. Chase, T...