421 search results - page 23 / 85 » Hardware efficient architectures for Eigenvalue computation |
MAM
2006
13 years 8 months ago
2006
Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the f...
MSS
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
ASAP
2003
IEEE
14 years 1 months ago
2003
IEEE
Recently, a number of researchers have started to investigate new video-on-demand (VoD) architectures using batching, patching and periodic broadcasting. These architectures, comp...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
ASAP
2008
IEEE
13 years 10 months ago
2008
IEEE
Arithmetic coding is an efficient entropy compression method that achieves results close to the entropy limit and it is used in modern standards such as JPEG-2000 and H.264. Arith...