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» Hardware efficient architectures for Eigenvalue computation
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ASAP
2008
IEEE
145views Hardware» more  ASAP 2008»
14 years 3 months ago
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system
This article discusses the design of an application specific MPSoC architecture dedicated to Multiple Target Tracking (MTT). This application has its utility in driver assistant s...
Jehangir Khan, Smaïl Niar, Atika Rivenq, Yass...
ERSA
2010
137views Hardware» more  ERSA 2010»
13 years 5 months ago
An Automated Scheduling and Partitioning Algorithm for Scalable Reconfigurable Computing Systems
As reconfigurable computing (RC) platforms are becoming increasingly large-scale and heterogeneous, efficiently scheduling and partitioning applications on these platforms is a gro...
Casey Reardon, Alan D. George, Greg Stitt, Herman ...
ISMVL
2005
IEEE
108views Hardware» more  ISMVL 2005»
14 years 2 months ago
Approaching the Physical Limits of Computing
As logic device sizes shrink towards the nanometer scale, a number of important physical limits threaten to soon halt further improvements in computer performance per unit cost. H...
Michael P. Frank
ISCAS
2003
IEEE
168views Hardware» more  ISCAS 2003»
14 years 1 months ago
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder
MPEG-4 Fine Granularity Scalability (FGS) provides bandwidth adaptation and error resilience features for streaming applications. In this paper. by estimating the required computa...
Chih-Wei Hsu, Yung-Chi Chang, Wei-Min Chao, Liang-...
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
14 years 23 days ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...