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» Hardware efficient architectures for Eigenvalue computation
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IJNSEC
2008
106views more  IJNSEC 2008»
13 years 8 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
CORR
2010
Springer
66views Education» more  CORR 2010»
13 years 7 months ago
Three-Level Parallel J-Jacobi Algorithms for Hermitian Matrices
The paper describes several efficient parallel implementations of the one-sided hyperbolic Jacobi-type algorithm for computing eigenvalues and eigenvectors of Hermitian matrices. ...
Sanja Singer, Sasa Singer, Vedran Novakovic, Davor...
ICMCS
2005
IEEE
136views Multimedia» more  ICMCS 2005»
14 years 2 months ago
Efficient Hardware Search Engine for Associative Content Retrieval of Long Queries in Huge Multimedia Databases
Due to the enormous increase in the stored digital contents, search and retrieval functionalities are necessary in multimedia systems. Though processor speed for standard PCs (Per...
Christophe Layer, Hans-Jörg Pfleiderer
FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
14 years 5 days ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 6 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias