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» Hardware implementation of a novel genetic algorithm
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IEEEPACT
2008
IEEE
14 years 2 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
14 years 26 days ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...
SIGMETRICS
2008
ACM
181views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Counter braids: a novel counter architecture for per-flow measurement
Fine-grained network measurement requires routers and switches to update large arrays of counters at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amo...
Yi Lu, Andrea Montanari, Balaji Prabhakar, Sarang ...
EUROGP
2005
Springer
115views Optimization» more  EUROGP 2005»
14 years 1 months ago
Genetic Programming in Wireless Sensor Networks
Abstract. Wireless sensor networks (WSNs) are medium scale manifestations of a paintable or amorphous computing paradigm. WSNs are becoming increasingly important as they attain gr...
Derek M. Johnson, Ankur Teredesai, Robert T. Salta...
FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
14 years 1 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...