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MICRO
1992
IEEE
128views Hardware» more  MICRO 1992»
13 years 11 months ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
14 years 3 days ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
CODES
1996
IEEE
13 years 11 months ago
Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated befor...
Jean Paul Calvez, Dominique Heller, Olivier Pasqui...
CAMP
2005
IEEE
14 years 1 months ago
Real-Time Low Level Feature Extraction for On-Board Robot Vision Systems
Abstract— Robot vision systems notoriously require large computing capabilities, rarely available on physical devices. Robots have limited embedded hardware, and almost all senso...
Roberto Pirrone, Giuseppe Careri, F. Saverio Fabia...
CASES
2009
ACM
14 years 2 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke