734 search results - page 141 / 147 » Hardware support for code integrity in embedded processors |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
ICPPW
2005
IEEE
14 years 1 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
The emergence of multicore processors has heightened the need for effective parallel programming practices. In addition to writing new parallel programs, the next generation of pr...
VALUETOOLS
2006
ACM
14 years 1 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...