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» Hiding Communication Latency in Data Parallel Applications
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ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
14 years 1 months ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...
ESCIENCE
2005
IEEE
14 years 1 months ago
Iteration Aware Prefetching for Remote Data Access
1 Although processing speed, storage capacity and network bandwidth are steadily increasing, network latency remains a bottleneck for scientists accessing large remote data sets. T...
Philip J. Rhodes, Sridhar Ramakrishnan
ANSS
1995
IEEE
13 years 11 months ago
Algorithms for categorizing multiprocessor communication under invalidate and update-based coherence protocols
In this paper we present simulation algorithmsthat characterize the main sources of communication generated by parallel applications under both invalidate and updatebased cache co...
Ricardo Bianchini, Leonidas I. Kontothanassis
ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
13 years 11 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
DAWAK
2003
Springer
14 years 1 months ago
Comprehensive Log Compression with Frequent Patterns
In this paper we present a comprehensive log compression (CLC) method that uses frequent patterns and their condensed representations to identify repetitive information from large ...
Kimmo Hätönen, Jean-François Boul...