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» Hierarchical Design of Fast Minimum Disagreement Algorithms
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DATE
2009
IEEE
118views Hardware» more  DATE 2009»
14 years 2 months ago
Gate sizing for large cell-based designs
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
Stephan Held
ICC
2007
IEEE
104views Communications» more  ICC 2007»
14 years 1 months ago
Joint Design of Tx-Rx Beamformers in MIMO Downlink Channel
We consider a single-cell multiple-input multiple-output (MIMO) downlink channel where linear transmission and reception strategy is employed. The base station (BS) transmitter is...
Marian Codreanu, Antti Tölli, Markku J. Juntt...
SIGCOMM
2009
ACM
14 years 2 months ago
Hash, don't cache: fast packet forwarding for enterprise edge routers
As forwarding tables and link speeds continue to grow, fast packet forwarding becomes increasingly challenging for enterprise edge routers. Simply building routers with ever large...
Minlan Yu, Jennifer Rexford
COMPGEOM
2004
ACM
14 years 1 months ago
A scalable simulator for forest dynamics
Models of forest ecosystems are needed to understand how climate and land-use change can impact biodiversity. In this paper we describe an individual-based, spatially-explicit for...
Sathish Govindarajan, Mike Dietze, Pankaj K. Agarw...
DAC
2005
ACM
14 years 8 months ago
Enhanced leakage reduction Technique by gate replacement
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
Lin Yuan, Gang Qu