251 search results - page 4 / 51 » Hierarchical Modeling and Simulation of Large Analog Circuit... |
COLT
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. We consider the problem of learning an acyclic discrete circuit with n wires, fan-in bounded by k and alphabet size s using value injection queries. For the class of tran...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— This paper presents ATLAS - a framework for automated analog circuit synthesis that comprises of both topology generation and subsequent circuit sizing. A hierarchically arrang...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
FCCM
2007
IEEE
14 years 1 months ago
2007
IEEE
— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. This p...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic b...