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» Hierarchical Simulation of a Multiprocessor Architecture
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ICS
2009
Tsinghua U.
14 years 2 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad
WICON
2008
13 years 11 months ago
A network mobility management scheme for fast QoS handover
The evolution of wireless access technologies has led to a new era of Mobile Internet. Network mobility, which considers the mobility of an entire network, is particularly suitabl...
Cheng-Wei Lee, Meng Chang Chen, Yeali S. Sun
IPPS
2010
IEEE
13 years 7 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
DAC
1999
ACM
14 years 1 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
HPCA
2009
IEEE
14 years 4 months ago
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
Pablo Abad Fidalgo, Valentin Puente, José-&...