Although other genres have used procedural level generation to extend gameplay and replayability, platformer games have not yet seen successful level generation. This paper propos...
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
In this paper we explore the network level architecture of distributed sensor systems that perform in-network processing. We propose a system with heterogeneous nodes that organiz...
Recently numerous proposals for modelling and querying Multidimensional Databases (MDDB) are proposed. Among the still open problems there is a rigorous classification of the diff...