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» Hierarchies and levels of reality
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AIIDE
2006
13 years 9 months ago
Procedural Level Design for Platform Games
Although other genres have used procedural level generation to extend gameplay and replayability, platformer games have not yet seen successful level generation. This paper propos...
Kate Compton, Michael Mateas
ISCAPDCS
2004
13 years 8 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 1 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
WSNA
2003
ACM
14 years 22 days ago
Computation hierarchy for in-network processing
In this paper we explore the network level architecture of distributed sensor systems that perform in-network processing. We propose a system with heterogeneous nodes that organiz...
Ram Kumar, Vlasios Tsiatsis, Mani B. Srivastava
DOLAP
1999
ACM
13 years 11 months ago
Characterization of Hierarchies and Some Operators in OLAP Environment
Recently numerous proposals for modelling and querying Multidimensional Databases (MDDB) are proposed. Among the still open problems there is a rigorous classification of the diff...
Elaheh Pourabbas, Maurizio Rafanelli