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SIGARCH
2008
96views more  SIGARCH 2008»
13 years 9 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
POLICY
2004
Springer
14 years 2 months ago
Policy-Based Mobile Ad Hoc Network Management
Ad hoc networking is the basis of the future military network-centric warfare architecture. Such networks are highly dynamic in nature, as mobile ad hoc networks are formed over w...
Ritu Chadha, Hong Cheng, Yuu-Heng Cheng, Cho-Yu Ja...
SIGMETRICS
2010
ACM
213views Hardware» more  SIGMETRICS 2010»
14 years 1 months ago
Small subset queries and bloom filters using ternary associative memories, with applications
Associative memories offer high levels of parallelism in matching a query against stored entries. We design and analyze an architecture which uses a single lookup into a Ternary C...
Ashish Goel, Pankaj Gupta
IEEEPACT
2000
IEEE
14 years 1 months ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
PATMOS
2005
Springer
14 years 2 months ago
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
Philippe Manet, David Bol, Renaud Ambroise, Jean-D...