12 search results - page 2 / 3 » High Level Synthesis Techniques for Efficient Built-In-Self ... |
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
ASPDAC
2008
ACM
14 years 26 days ago
2008
ACM
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
VLSID
1999
IEEE
14 years 3 months ago
1999
IEEE
Formal approaches to HW and system design have not been generally adopted, because designers often view the modelling concepts in these approaches as unsuitable for their problems...
MSO
2003
14 years 6 days ago
2003
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
IJVR
2006
13 years 10 months ago
2006
In this paper, we will present an overview of existing research in the vast area of IVH systems. We will also present our ongoing work on improving the expressive capabilities of I...