88 search results - page 14 / 18 » High Level Synthesis from Sim-nML Processor Models |
DAC
2009
ACM
14 years 11 days ago
2009
ACM
We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
FASE
2003
Springer
14 years 27 days ago
2003
Springer
Scenarios are powerful tools to model and analyze software systems. However, since they do not provide a complete description of the system, but just some possible execution paths,...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
In 2002, Japan announced the Earth Simulator—a supercomputer based on low-volume vector processors and a custom network—and reported that computational scientists had used it ...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...