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DAC
1992
ACM
14 years 2 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
CGO
2009
IEEE
14 years 5 months ago
OptiScope: Performance Accountability for Optimizing Compilers
Compilers employ many aggressive code transformations to achieve highly optimized code. However, because of complex target architectures and unpredictable optimization interaction...
Tipp Moseley, Dirk Grunwald, Ramesh Peri
SAMOS
2004
Springer
14 years 4 months ago
High-Speed Event-Driven RTL Compiled Simulation
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Alexey Kupriyanov, Frank Hannig, Jürgen Teich
CASES
2006
ACM
14 years 4 months ago
Automatic performance model construction for the fast software exploration of new hardware designs
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
John Cavazos, Christophe Dubach, Felix V. Agakov, ...
EUNIS
2001
14 years 7 days ago
High Performance Computing in Europe and USA: A Comparison
Since 1993 we compile and publish twice a year a list of the mostpowerful supercomputers in the world. In this article we compare the situation of High-Performance Computing (HPC)...
Erich Strohmaier, Hans Werner Meuer