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ICS
1998
Tsinghua U.
15 years 8 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
ICCCN
1997
IEEE
15 years 8 months ago
Design and implementation of a QoS capable switch-router
Rapid expansion has strained the capabilities of the Internet infrastructure. Emerging audio and video applications place further demands on already overloaded network elements, e...
Erol Basturk, Alexander Birman, G. Delp, Roch Gu&e...
ICDCS
1997
IEEE
15 years 8 months ago
Load Profiling In Distributed Real-Time Systems
Load balancing is often used to ensure that nodes in a distributed systems are equally loaded. In this paper, we show that for real-time systems, load balancing is not desirable. ...
Azer Bestavros
134
Voted
INFOCOM
1997
IEEE
15 years 8 months ago
Analysis of Queueing Displacement Using Switch Port Speedup
Current high-speed packet switching systems, ATM in particular, have large port bu ering requirements. The use of highly integrated ASIC technology for implementing high-degree an...
Israel Cidon, Asad Khamisy, Moshe Sidi
131
Voted
IUI
1997
ACM
15 years 8 months ago
Helping Users Think in Three Dimensions: Steps Toward Incorporating Spatial Cognition in User Modelling
Historically, efforts at user modelling in educational systems have tended to employ knowledge representations in which symbolic (or "linguistic") cognition is emphasize...
Michael Eisenberg, Ann Nishioka, M. E. Schreiner
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