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CODES
2001
IEEE
14 years 2 months ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
12 years 1 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
IEEEPACT
2000
IEEE
14 years 3 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
SIGPRO
2010
103views more  SIGPRO 2010»
13 years 9 months ago
Optimal design of high-performance separable wavelet filter banks for image coding
An optimization-based method is proposed for the design of high-performance separable wavelet filter banks for image coding. This method yields linear-phase perfect-reconstructio...
Michael D. Adams, Di Xu
ASPLOS
1996
ACM
14 years 3 months ago
Exploiting Dual Data-Memory Banks in Digital Signal Processors
Over the past decade, digital signal processors (DSPs) have emerged as the processors of choice for implementing embedded applications in high-volume consumer products. Through th...
Mazen A. R. Saghir, Paul Chow, Corinna G. Lee