174 search results - page 20 / 35 » High Performance FPGA Implementation of the Mersenne Twister |
FCCM
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high per...
FCCM
2009
IEEE
14 years 2 months ago
2009
IEEE
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
FPGA
2004
ACM
14 years 26 days ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract—Deep packet inspection (DPI) is often used in network intrusion detection and prevention systems (NIDPS), where incoming packet payloads are compared against known attac...