174 search results - page 3 / 35 » High Performance FPGA Implementation of the Mersenne Twister |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC’s 0.18μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic ...
JUCS
2007
13 years 7 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
AHS
2007
IEEE
13 years 7 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining...