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ICVS
2001
Springer
14 years 7 days ago
Compiling SA-C Programs to FPGAs: Performance Results
Abstract. At the first ICVS, we presented SA-C (“sassy”), a singleassignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallel...
Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hamm...
ISCAPDCS
2007
13 years 9 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
ISCAS
2008
IEEE
141views Hardware» more  ISCAS 2008»
14 years 2 months ago
ASPA: Focal Plane digital processor array with asynchronous processing capabilities
— In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits fr...
Alexey Lopich, Piotr Dudek
FPL
2010
Springer
170views Hardware» more  FPL 2010»
13 years 5 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
IPPS
2007
IEEE
14 years 2 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones