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MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
14 years 1 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
IPPS
2009
IEEE
14 years 2 months ago
Exploring the effect of block shapes on the performance of sparse kernels
In this paper we explore the impact of the block shape on blocked and vectorized versions of the Sparse Matrix-Vector Multiplication (SpMV) kernel and build upon previous work by ...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...
ICA
2007
Springer
14 years 1 months ago
Hierarchical ALS Algorithms for Nonnegative Matrix and 3D Tensor Factorization
In the paper we present new Alternating Least Squares (ALS) algorithms for Nonnegative Matrix Factorization (NMF) and their extensions to 3D Nonnegative Tensor Factorization (NTF) ...
Andrzej Cichocki, Rafal Zdunek, Shun-ichi Amari
SEKE
2007
Springer
14 years 1 months ago
Improving Separation of Concerns in the Development of Scientific Applications
High performance computing (HPC) is gaining popularity in solving scientific applications. Using the current programming standards, however, it takes an HPC expert to efficiently ...
Seyed Masoud Sadjadi, J. Martínez, T. Soldo...
NOSSDAV
2004
Springer
14 years 1 months ago
Reduced state fair queuing for edge and core routers
Despite many years of research, fair queuing still faces a number of implementation challenges in high speed routers. In particular, in spite of proposals such as DiffServ, the st...
Ramana Rao Kompella, George Varghese