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» High Performance Matrix Multiplication on Many Cores
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VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 9 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
CCGRID
2010
IEEE
13 years 10 months ago
Asynchronous Communication Schemes for Finite Difference Methods on Multiple GPUs
Finite difference methods continue to provide an important and parallelisable approach to many numerical simulations problems. Iterative multigrid and multilevel algorithms can co...
Daniel P. Playne, Kenneth A. Hawick
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
14 years 3 months ago
Collaborative Routing Architecture for FPGA
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
Yaling Ma, Mingjie Lin
TON
2010
97views more  TON 2010»
13 years 3 months ago
Gradually reconfiguring virtual network topologies based on estimated traffic matrices
Traffic matrix, which is required as an input of traffic engineering (TE) methods, is difficult to be obtained directly. One possible approach to obtaining the traffic matrix is to...
Yuichi Ohsita, Takashi Miyamura, Shin'ichi Arakawa...
SMA
2009
ACM
163views Solid Modeling» more  SMA 2009»
14 years 3 months ago
Multi-core collision detection between deformable models
We present a new parallel algorithm for interactive and continuous collision detection between deformable models. Our algorithm performs incremental hierarchical computations betw...
Min Tang, Dinesh Manocha, Ruofeng Tong