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MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 2 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
OSDI
2006
ACM
14 years 7 months ago
Fidelity and Yield in a Volcano Monitoring Sensor Network
We present a science-centric evaluation of a 19-day sensor network deployment at Reventador, an active volcano in Ecuador. Each of the 16 sensors continuously sampled seismic and ...
Geoffrey Werner-Allen, Konrad Lorincz, Jeff Johnso...
VLSISP
2008
129views more  VLSISP 2008»
13 years 7 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...
PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
DAC
2007
ACM
14 years 8 months ago
A New Twisted Differential Line Structure in Global Bus Design
Twisted differential line structure can effectively reduce crosstalk noise on global bus, which foresees a wide applicability. However, measured performance based on fabricated ci...
Zhanyuan Jiang, Shiyan Hu, Weiping Shi