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FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
15 years 8 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
GLOBECOM
2009
IEEE
15 years 6 months ago
Iterative Versus Adaptive Equalizers in Time-Variant Channels
—This paper discusses the application of iterative versus adaptive equalizers to a Universal Mobile Telecommunications System (UMTS) High Speed Downlink Packet Access (HSDPA) rec...
Clemens Buchacher, Joachim Wehinger, Mario Huemer
ISCAS
2006
IEEE
99views Hardware» more  ISCAS 2006»
15 years 9 months ago
High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor
— By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error ra...
Hao Zhong, Tong Zhang, Erich F. Haratsch
IWCMC
2010
ACM
15 years 5 months ago
Joint network coding and beamforming techniques for downlink channels
We propose a joint optimization of Network Coding and MIMO techniques to improve the downlink channel throughput of a wireless base station. Specifically, we consider a MIMO base...
Monchai Lertsutthiwong, Thinh Nguyen, Bechir Hamda...
TPDS
2002
105views more  TPDS 2002»
15 years 2 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills