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» High Speed Digital Filtering on SRAM-Based FPGAs
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VLSID
1994
IEEE
82views VLSI» more  VLSID 1994»
14 years 3 months ago
High Speed Digital Filtering on SRAM-Based FPGAs
A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghosha...
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
14 years 3 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
IEICET
2008
106views more  IEICET 2008»
13 years 11 months ago
Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Comm
Finite impulse response (FIR) filtering is the most computationally intensive operation in the channelizer of a wireless communication receiver. Higher order FIR channel filters a...
Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund ...
WCE
2007
14 years 14 hour ago
VHDL Implementation of Multiplierless, High Performance DWT Filter Bank
—The JPEG 2000 image coding standard employs the biorthogonal 9/7 wavelet for lossy compression. The performance of hardware implementation of 9/7-filter bank depends on accuracy...
M. M. Aswale, R. B. Patil